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> ios版最终幻想4，二周目获得的能力 突破极限怎么用
ios版最终幻想4，二周目获得的能力 突破极限怎么用
转载 编辑：李强
为了帮助网友解决“ios版最终幻想4，二周目获得的能力 突”相关的问题，中国学网通过互联网对“ios版最终幻想4，二周目获得的能力 突”相关的解决方案进行了整理,用户详细问题包括:RT,我想知道:ios版最终幻想4，二周目获得的能力 突破极限怎么用，具体解决方案如下：解决方案1：就是伤害和血量魔量的上限加一位。通过对数据库的索引,我们还为您准备了：答：就是伤害和血量魔量的上限加一位。===========================================答：是的，所谓二周目就是第一次通关后，再重新开始玩第二次。这个第二次玩这个游戏在日语里就叫二周目很多日本游戏玩二周目的时候会有额外的奖励062当然得是在同一台机器上395或者继承同一个一周目通关存档===========================================问：有二周目吗？什么是二周目？我剧情已经通关了，是不是接下来重新打就算...答：是的，所谓二周目就是第一次通关后，再重新开始玩第二次。这个第二次玩这个游戏在日语里就叫二周目 很多日本游戏玩二周目的时候会有额外的奖励，当然得是在同一台机器上，或者继承同一个一周目通关存档===========================================问：如题，通关后命名威出现说什么开始第二轮游戏，稀有装备会保存，结果我...答：别紧张……好吧，不舍得也没有办法，因为FF4二周目能继承的也就那么些能传承的东西，其他嘛……【系统设定二周目从头开始，让你继承了技能和几件好装备不错了】神马的我是绝对不会乱说的，所以亲别紧张了，反正真正值钱的也就是你辛辛苦苦刷出来的那...===========================================问：如题，通关后命名威出现说什么开始第二轮游戏，稀有装备会保存，结果我...答：2周目，3周目的隐藏迷宫吧？打最终BOSS的BOSS最终的形式忍者的事情时，他偷了被称为暗物质，两个星期的网格，用它在脸上触发。 阿尔法 Alpha===========================================问：还是没爆炸……答：能力就靠喂书，支线，地上捡啊，全部能力要到2周目才能收集全，去天幻看看/items2.htm#twins 学就是“能力”里面 调出来呀，除掉 “道具”不能更换，还可以自定义5个 我的是 主角：攻击（自动），诱敌，反击，HP+50%，白魔法 ...===========================================问：还是没爆炸……答：我是都喂了，不过2,3周目技能多，喂就是了===========================================问：1，洋葱套有什么用？2，传说之剑怎么磨砺，成就上说有。。3，那对双胞胎...答：1：洋葱套是后期刷不同的怪掉落的尾巴去换的，可以多周目继承，很强的一套装备 2：传说之剑磨砺应该说的是 石中剑任务，在地下世界左下角幻兽洞里面的幻兽镇有个箱子可以拿到老鼠尾巴，然后去地上世界右边的精金洞换成精金石，然后回地下世界右...===========================================问：1，洋葱套有什么用？2，传说之剑怎么磨砺，成就上说有。。3，那对双胞胎...答：1 巴隆城、2 迷雾洞窟、3 凯波、4 法尔布城、5 试炼山南边的陆行鸟之森、6 巴隆镇武器防具店、7 特罗亚镇（对话完后要去酒吧）、8 阿卡尔特村（要给他彩虹布丁，需要打布丁系怪兽掉落的稀有道具）、9 地下矮人城酒吧（需要对话两次进入战斗）、1...=========================================== 就是伤害和血量魔量的上限加一位。===========================================别紧张……好吧,不舍得也没有办法,因为FF4二周目能继承的也就那么些能传承的东西,其他嘛……【系统设定二周目从头开始,让你继承了技能和几件好装备不错了】神马的我是...===========================================脚踢和忍耐,同样需要给他吃2个技能书 最后就是月老了,给他吃2个技能,到进最后迷宫... 拿鞭子可以把很多怪打到麻痹,不能动,然后纯虐),黑魔法,快速吟唱(3周目,2周目要给白魔...===========================================以2下q是天z幻3论坛心7得总结,包括技能道具的最终队6伍的固定五q人u,塞西尔(セ)是高... 2使用的技能。以4下f为8比2较符合这五l个q人a成长2和能力o特点的技能道具搭配: セ:...===========================================人族黑魔道士;恩莫族、人族幻术士;恩莫族、莫古利族时魔道士白魔杖 - 人族、维埃拉、恩莫族白魔道士;维埃拉族召唤士;邦加族武僧刀(武士刀)- 人族忍者、维埃拉族刺客突刺...===========================================可以。 在最终的那个白色房子往回走,两个传送门分别去11和12章。 还可以用传送门可以到下界去。 而且水晶第十级解放,在这里增加的能力是最多的啦。===========================================这是部分使用ACG汉化组零式作品的玩家会碰上的BUG,给楼主几个解决方案:1.重新安装游戏再运行。2.更换天幻的合盘版(自己真心觉得天幻汉化的零式字体效果没有ACG的好...===========================================好像是通关后可以选择继承能力的新游戏,怪物等级会变高。但我还没通,尚不能证实===========================================这样4人组全了。记得人物能力是根据你通关时候这些人离队时候能力,所以要练强一些... 路不复杂,可以得到最强一套装备,但是都有强力BOSS守护。 怪物能力比主角队伍进入...===========================================也比较容易得到。 用道具来制作圣战之药/英雄之药,是非常不现实的,除非你修改,否则要凑齐一个药的材料都非常困难。 最实在的方法,是利用第一只雷鸟召唤兽的能力卡片精制...===========================================
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鼓捣enc28j60这个模块过程还是比较曲折的！
买这个模块的时候，卖家只附送了51的驱动工程。或者说，就51的工程能用！
在51上，一编译一下载就搞定了！
========================吐槽下==============================
在F4这个平台上呢！因为enc28j60.c这个文件的问题，导致我创建了20多份不同的工程来测试！比较坑爹！
刚开始的时候，想移植51的这个文件，发现改动量太大了，改了一下，测试不成功就放弃之！
再拿野火stm32f103的来移植，还是不成功。发现也有网友有这问题，我跟踪调试，发现mac初始化一直不成功！
只好去拿官方库里面的 lwip 的工程来改。还是不行！ 这下不淡定了！
打算去收集资料！
百度关键字 stm32f4 enc28j60&，几乎没可用的资料！有的也是用手指头都能数的完的求助贴！
谷歌关键字 stm32f4 enc28j60&，有惊喜！能看到几个视频，而且要看还得翻墙！
那就翻吧！废了九牛二虎之力，找到了三份源码！其中日本那份下载不了，另外两份倒是下载了。
但是打开一看，又纠结了，一份是linux下的工程。另一份不知道拿什么开发工具写的。不过这两份源码倒是能用！
----------------------------------------------------------------------------------------------------
重新看了一遍enc28j60的手册，拿之前lcd的工程加上国外的源码重新写吧！
前前后后弄了两天，终于出来了！深感累到不行！
============================END=============================
说点有用的，enc28j60与f4通信比较简单。使用SPI，也就需要四根线就行了。
我的接法是：
PA4 -------------- CS
PA5 -------------- SCK
PA6 -------------- SO
PA7 -------------- SI
ENC28J60.C
#include &ENC28J60.h&
#include &spi.h&
#include &lcd.h&
static uint8_t Enc28j60B
static uint16_t gNextPacketP
static uint8_
unsigned char ENC28J60_SendByte(unsigned char dt)
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI_I2S_SendData(SPI1, dt);
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
return SPI_I2S_ReceiveData(SPI1);
uint8_t enc28j60ReadOp(uint8_t op, uint8_t address)
// issue read command
ENC28J60_SendByte(op | (address & ADDR_MASK));
temp = ENC28J60_SendByte(0xFF);
if (address & 0x80)
temp = ENC28J60_SendByte(0xFF);
// release CS
void enc28j60WriteOp(uint8_t op, uint8_t address, uint8_t data)
ENC28J60_SendByte(op | (address & ADDR_MASK));
ENC28J60_SendByte(data);
void enc28j60PowerDown() {
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
while(enc28j60Read(ESTAT) & ESTAT_RXBUSY);
while(enc28j60Read(ECON1) & ECON1_TXRTS);
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PWRSV);
void enc28j60PowerUp() {
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON2, ECON2_PWRSV);
while(!enc28j60Read(ESTAT) & ESTAT_CLKRDY);
void enc28j60ReadBuffer(uint16_t len, uint8_t* data)
ENC28J60_SendByte(ENC28J60_READ_BUF_MEM);
while (len--) {
*data++ = ENC28J60_SendByte(0x00);
// Remove next line suggested by user epam - not needed
*data='\0';
static uint16_t enc28j60ReadBufferWord() {
enc28j60ReadBuffer(2, (uint8_t*) &result);
void enc28j60WriteBuffer(uint16_t len, uint8_t* data)
ENC28J60_SendByte(ENC28J60_WRITE_BUF_MEM);
while (len--)
ENC28J60_SendByte(*data++);
void enc28j60SetBank(uint8_t address)
if ((address & BANK_MASK) != Enc28j60Bank) {
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_BSEL1|ECON1_BSEL0);
Enc28j60Bank = address & BANK_MASK;
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, Enc28j60Bank&&5);
uint8_t enc28j60Read(uint8_t address)
// set the bank
enc28j60SetBank(address);
// do the read
return enc28j60ReadOp(ENC28J60_READ_CTRL_REG, address);
void enc28j60WriteWord(uint8_t address, uint16_t data) {
enc28j60Write(address, data & 0xff);
enc28j60Write(address + 1, data && 8);
// read upper 8 bits
uint16_t enc28j60PhyReadH(uint8_t address)
// Set the right address and start the register read operation
enc28j60Write(MIREGADR, address);
enc28j60Write(MICMD, MICMD_MIIRD);
delay_us(15);
// wait until the PHY read completes
while(enc28j60Read(MISTAT) & MISTAT_BUSY);
// reset reading bit
enc28j60Write(MICMD, 0x00);
return (enc28j60Read(MIRDH));
void enc28j60Write(uint8_t address, uint8_t data)
// set the bank
enc28j60SetBank(address);
// do the write
enc28j60WriteOp(ENC28J60_WRITE_CTRL_REG, address, data);
void enc28j60PhyWrite(uint8_t address, uint16_t data)
// set the PHY register address
enc28j60Write(MIREGADR, address);
// write the PHY data
enc28j60Write(MIWRL, data);
enc28j60Write(MIWRH, data&&8);
// wait until the PHY write completes
while(enc28j60Read(MISTAT) & MISTAT_BUSY){
delay_us(15);
static void enc28j60PhyWriteWord(byte address, word data) {
enc28j60Write(MIREGADR, address);
//enc28j60WriteByte(MIREGADR, address);
enc28j60WriteWord(MIWRL, data);
while (enc28j60ReadByte(MISTAT) & MISTAT_BUSY)
void enc28j60clkout(uint8_t clk)
//setup clkout: 2 is 12.5MHz:
enc28j60Write(ECOCON, clk & 0x7);
void enc28j60Init( uint8_t* macaddr )
enableC // ss=0
// perform system reset
enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
delay_ms(50);
// check CLKRDY bit to see if reset is complete
// The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait.
//while(!(enc28j60Read(ESTAT) & ESTAT_CLKRDY));
// do bank 0 stuff
// initialize receive buffer
// 16-bit transfers, must write low byte first
// set receive buffer start address
gNextPacketPtr = RXSTART_INIT;
// Rx start
enc28j60WriteWord(ERXSTL, RXSTART_INIT);
// set receive pointer address
enc28j60WriteWord(ERXRDPTL, RXSTART_INIT);
enc28j60WriteWord(ERXNDL, RXSTOP_INIT);
// TX start
enc28j60WriteWord(ETXSTL, TXSTART_INIT);
enc28j60WriteWord(ETXNDL, TXSTOP_INIT);
// do bank 1 stuff, packet filter:
// For broadcast packets we allow only ARP packtets
// All other packets should be unicast only for our mac (MAADR)
// The pattern to match on is therefore
// 06 08 -- ff ff ff ff ff ff -& ip checksum for theses bytes=f7f9
// in binary these poitions are:11 11
// This is hex 303F-&EPMM0=0x3f,EPMM1=0x30
//enc28j60Write(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN);
//Change to add ERXFCON_BCEN recommended by epam
//enc28j60Write(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN);
ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN;
enc28j60Write(ERXFCON, erxfcon );
enc28j60WriteWord(EPMM0, 0x303f);
enc28j60WriteWord(EPMCSL, 0xf7f9);
// do bank 2 stuff
// enable MAC receive
enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
// bring MAC out of reset
enc28j60Write(MACON2, 0x00);
// enable automatic padding to 60bytes and CRC operations
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
//|MACON3_FULDPX);
// set inter-frame gap (non-back-to-back)
enc28j60WriteWord(MAIPGL, 0x0C12);
// set inter-frame gap (back-to-back)
enc28j60Write(MABBIPG, 0x12);
// Set the maximum packet size which the controller will accept
// Do not send packets longer than MAX_FRAMELEN:
enc28j60WriteWord(MAMXFLL, MAX_FRAMELEN);
// do bank 3 stuff
// write MAC address
// NOTE: MAC address in ENC28J60 is byte-backward
enc28j60Write(MAADR5, macaddr[0]);
enc28j60Write(MAADR4, macaddr[1]);
enc28j60Write(MAADR3, macaddr[2]);
enc28j60Write(MAADR2, macaddr[3]);
enc28j60Write(MAADR1, macaddr[4]);
enc28j60Write(MAADR0, macaddr[5]);
// no loopback of transmitted frames
enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS);
// switch to bank 0
enc28j60SetBank(ECON1);
// enable interrutps
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
// enable packet reception
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
LCD_String(20,80,&Mac Init&,GREEN);
// read the revision of the chip:
uint8_t enc28j60getrev(void)
rev=enc28j60Read(EREVID);
// microchip forgot to step the number on the silcon when they
// released the revision B7. 6 is now rev B7. We still have
// to see what they do when they release B8. At the moment
// there is no B8 out yet
if (rev&5) rev++;
return(rev);
// A number of utility functions to enable/disable broadcast and multicast bits
void enc28j60EnableBroadcast( void ) {
erxfcon |= ERXFCON_BCEN;
enc28j60Write(ERXFCON, erxfcon);
void enc28j60DisableBroadcast( void ) {
erxfcon &= (0xff ^ ERXFCON_BCEN);
enc28j60Write(ERXFCON, erxfcon);
void enc28j60EnableMulticast( void ) {
erxfcon |= ERXFCON_MCEN;
enc28j60Write(ERXFCON, erxfcon);
void enc28j60DisableMulticast( void ) {
erxfcon &= (0xff ^ ERXFCON_MCEN);
enc28j60Write(ERXFCON, erxfcon);
// link status
uint8_t enc28j60linkup(void)
// bit 10 (= bit 3 in upper reg)
return(enc28j60PhyReadH(PHSTAT2) && 4);
void enc28j60PacketSend(uint16_t len, uint8_t* packet)
// Check no transmit in progress
while (enc28j60ReadOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_TXRTS)
// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
if( (enc28j60Read(EIR) & EIR_TXERIF) ) {
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
// Set the write pointer to start of transmit buffer area
enc28j60WriteWord(EWRPTL, TXSTART_INIT);
// Set the TXND pointer to correspond to the packet size given
enc28j60WriteWord(ETXNDL, (TXSTART_INIT+len));
// write per-packet control byte (0x00 means use macon3 settings)
enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
// copy the packet into the transmit buffer
enc28j60WriteBuffer(len, packet);
// send the contents of the transmit buffer onto the network
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
// just probe if there might be a packet
//uint8_t enc28j60hasRxPkt(void)
return enc28j60ReadByte(EPKTCNT) & 0;
// Gets a packet from the network receive buffer, if one is available.
// The packet will by headed by an ethernet header.
The maximum acceptable length of a retrieved packet.
Pointer where packet data should be stored.
// Returns: Packet length in bytes if a packet was retrieved, zero otherwise.
uint16_t enc28j60PacketReceive(uint16_t maxlen, uint8_t* packet)
// check if a packet has been received and buffered
//if( !(enc28j60Read(EIR) & EIR_PKTIF) ){
// The above does not work. See Rev. B4 Silicon Errata point 6.
if( enc28j60Read(EPKTCNT) ==0 ){
return(0);
// Set the read pointer to the start of the received packet
enc28j60WriteWord(ERDPTL, gNextPacketPtr);
//enc28j60Write(ERDPTL, (gNextPacketPtr &0xFF));
//enc28j60Write(ERDPTH, (gNextPacketPtr)&&8);
// read the next packet pointer
gNextPacketPtr
= enc28j60ReadBufferWord();
//gNextPacketPtr
= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
//gNextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)&&8;
// read the packet length (see datasheet page 43)
len = enc28j60ReadBufferWord() - 4;
//len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
//len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)&&8;
//len-=4; //remove the CRC count
// read the receive status (see datasheet page 43)
= enc28j60ReadBufferWord();
= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
//rxstat |= ((uint16_t)enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0))&&8;
// limit retrieve length
if (len&maxlen-1){
len=maxlen-1;
// check CRC and symbol errors (see datasheet page 44, table 7-3):
// The ERXFCON.CRCEN is set by default. Normally we should not
// need to check this.
if ((rxstat & 0x80)==0){
// invalid
// copy the packet from the receive buffer
enc28j60ReadBuffer(len, packet);
// Move the RX read pointer to the start of the next received packet
// This frees the memory we just read out
enc28j60WriteWord(ERXRDPTL, gNextPacketPtr );
//enc28j60Write(ERXRDPTL, (gNextPacketPtr &0xFF));
//enc28j60Write(ERXRDPTH, (gNextPacketPtr)&&8);
// However, compensate for the errata point 13, rev B4: enver write an even address!
if ((gNextPacketPtr - 1 & RXSTART_INIT)
|| (gNextPacketPtr -1 & RXSTOP_INIT)) {
enc28j60WriteWord(ERXRDPTL, RXSTOP_INIT);
//enc28j60Write(ERXRDPTL, (RXSTOP_INIT)&0xFF);
//enc28j60Write(ERXRDPTH, (RXSTOP_INIT)&&8);
enc28j60WriteWord(ERXRDPTL, (gNextPacketPtr-1));
//enc28j60Write(ERXRDPTL, (gNextPacketPtr-1)&0xFF);
//enc28j60Write(ERXRDPTH, (gNextPacketPtr-1)&&8);
// decrement the packet counter indicate we are done with this packet
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
return(len);
ENC28J60.H
#ifndef __ENC28J60_H
#define __ENC28J60_H
#include &stm32f4xx.h&
#include &Delay.h&
#define disableChip
GPIO_SetBits(GPIOA,GPIO_Pin_4); delay_us(2);
#define enableChip
GPIO_ResetBits(GPIOA,GPIO_Pin_4); delay_us(2);
// ENC28J60 Control Registers
// Control register definitions are a combination of address,
// bank number, and Ethernet/MAC/PHY indicator bits.
// - Register address
(bits 0-4)
// - Bank number
(bits 5-6)
// - MAC/PHY indicator
#define ADDR_MASK
#define BANK_MASK
#define SPRD_MASK
// All-bank registers
#define EIE
#define EIR
#define ESTAT
#define ECON2
#define ECON1
// Bank 0 registers
#define ERDPTL
(0x00|0x00)
#define ERDPTH
(0x01|0x00)
#define EWRPTL
(0x02|0x00)
#define EWRPTH
(0x03|0x00)
#define ETXSTL
(0x04|0x00)
#define ETXSTH
(0x05|0x00)
#define ETXNDL
(0x06|0x00)
#define ETXNDH
(0x07|0x00)
#define ERXSTL
(0x08|0x00)
#define ERXSTH
(0x09|0x00)
#define ERXNDL
(0x0A|0x00)
#define ERXNDH
(0x0B|0x00)
#define ERXRDPTL
(0x0C|0x00)
#define ERXRDPTH
(0x0D|0x00)
#define ERXWRPTL
(0x0E|0x00)
#define ERXWRPTH
(0x0F|0x00)
#define EDMASTL
(0x10|0x00)
#define EDMASTH
(0x11|0x00)
#define EDMANDL
(0x12|0x00)
#define EDMANDH
(0x13|0x00)
#define EDMADSTL
(0x14|0x00)
#define EDMADSTH
(0x15|0x00)
#define EDMACSL
(0x16|0x00)
#define EDMACSH
(0x17|0x00)
// Bank 1 registers
#define EHT0
(0x00|0x20)
#define EHT1
(0x01|0x20)
#define EHT2
(0x02|0x20)
#define EHT3
(0x03|0x20)
#define EHT4
(0x04|0x20)
#define EHT5
(0x05|0x20)
#define EHT6
(0x06|0x20)
#define EHT7
(0x07|0x20)
#define EPMM0
(0x08|0x20)
#define EPMM1
(0x09|0x20)
#define EPMM2
(0x0A|0x20)
#define EPMM3
(0x0B|0x20)
#define EPMM4
(0x0C|0x20)
#define EPMM5
(0x0D|0x20)
#define EPMM6
(0x0E|0x20)
#define EPMM7
(0x0F|0x20)
#define EPMCSL
(0x10|0x20)
#define EPMCSH
(0x11|0x20)
#define EPMOL
(0x14|0x20)
#define EPMOH
(0x15|0x20)
#define EWOLIE
(0x16|0x20)
#define EWOLIR
(0x17|0x20)
#define ERXFCON
(0x18|0x20)
#define EPKTCNT
(0x19|0x20)
// Bank 2 registers
#define MACON1
(0x00|0x40|0x80)
#define MACON2
(0x01|0x40|0x80)
#define MACON3
(0x02|0x40|0x80)
#define MACON4
(0x03|0x40|0x80)
#define MABBIPG
(0x04|0x40|0x80)
#define MAIPGL
(0x06|0x40|0x80)
#define MAIPGH
(0x07|0x40|0x80)
#define MACLCON1
(0x08|0x40|0x80)
#define MACLCON2
(0x09|0x40|0x80)
#define MAMXFLL
(0x0A|0x40|0x80)
#define MAMXFLH
(0x0B|0x40|0x80)
#define MAPHSUP
(0x0D|0x40|0x80)
#define MICON
(0x11|0x40|0x80)
#define MICMD
(0x12|0x40|0x80)
#define MIREGADR
(0x14|0x40|0x80)
#define MIWRL
(0x16|0x40|0x80)
#define MIWRH
(0x17|0x40|0x80)
#define MIRDL
(0x18|0x40|0x80)
#define MIRDH
(0x19|0x40|0x80)
// Bank 3 registers
#define MAADR1
(0x00|0x60|0x80)
#define MAADR0
(0x01|0x60|0x80)
#define MAADR3
(0x02|0x60|0x80)
#define MAADR2
(0x03|0x60|0x80)
#define MAADR5
(0x04|0x60|0x80)
#define MAADR4
(0x05|0x60|0x80)
#define EBSTSD
(0x06|0x60)
#define EBSTCON
(0x07|0x60)
#define EBSTCSL
(0x08|0x60)
#define EBSTCSH
(0x09|0x60)
#define MISTAT
(0x0A|0x60|0x80)
#define EREVID
(0x12|0x60)
#define ECOCON
(0x15|0x60)
#define EFLOCON
(0x17|0x60)
#define EPAUSL
(0x18|0x60)
#define EPAUSH
(0x19|0x60)
// PHY registers
#define PHCON1
#define PHSTAT1
#define PHHID1
#define PHHID2
#define PHCON2
#define PHSTAT2
#define PHIE
#define PHIR
#define PHLCON
// ENC28J60 ERXFCON Register Bit Definitions
#define ERXFCON_UCEN
#define ERXFCON_ANDOR
#define ERXFCON_CRCEN
#define ERXFCON_PMEN
#define ERXFCON_MPEN
#define ERXFCON_HTEN
#define ERXFCON_MCEN
#define ERXFCON_BCEN
// ENC28J60 EIE Register Bit Definitions
#define EIE_INTIE
#define EIE_PKTIE
#define EIE_DMAIE
#define EIE_LINKIE
#define EIE_TXIE
#define EIE_WOLIE
#define EIE_TXERIE
#define EIE_RXERIE
// ENC28J60 EIR Register Bit Definitions
#define EIR_PKTIF
#define EIR_DMAIF
#define EIR_LINKIF
#define EIR_TXIF
#define EIR_WOLIF
#define EIR_TXERIF
#define EIR_RXERIF
// ENC28J60 ESTAT Register Bit Definitions
#define ESTAT_INT
#define ESTAT_LATECOL
#define ESTAT_RXBUSY
#define ESTAT_TXABRT
#define ESTAT_CLKRDY
// ENC28J60 ECON2 Register Bit Definitions
#define ECON2_AUTOINC
#define ECON2_PKTDEC
#define ECON2_PWRSV
#define ECON2_VRPS
// ENC28J60 ECON1 Register Bit Definitions
#define ECON1_TXRST
#define ECON1_RXRST
#define ECON1_DMAST
#define ECON1_CSUMEN
#define ECON1_TXRTS
#define ECON1_RXEN
#define ECON1_BSEL1
#define ECON1_BSEL0
// ENC28J60 MACON1 Register Bit Definitions
#define MACON1_LOOPBK
#define MACON1_TXPAUS
#define MACON1_RXPAUS
#define MACON1_PASSALL
#define MACON1_MARXEN
// ENC28J60 MACON2 Register Bit Definitions
#define MACON2_MARST
#define MACON2_RNDRST
#define MACON2_MARXRST
#define MACON2_RFUNRST
#define MACON2_MATXRST
#define MACON2_TFUNRST
// ENC28J60 MACON3 Register Bit Definitions
#define MACON3_PADCFG2
#define MACON3_PADCFG1
#define MACON3_PADCFG0
#define MACON3_TXCRCEN
#define MACON3_PHDRLEN
#define MACON3_HFRMLEN
#define MACON3_FRMLNEN
#define MACON3_FULDPX
// ENC28J60 MICMD Register Bit Definitions
#define MICMD_MIISCAN
#define MICMD_MIIRD
// ENC28J60 MISTAT Register Bit Definitions
#define MISTAT_NVALID
#define MISTAT_SCAN
#define MISTAT_BUSY
// ENC28J60 PHY PHCON1 Register Bit Definitions
#define PHCON1_PRST
#define PHCON1_PLOOPBK
#define PHCON1_PPWRSV
#define PHCON1_PDPXMD
// ENC28J60 PHY PHSTAT1 Register Bit Definitions
#define PHSTAT1_PFDPX
#define PHSTAT1_PHDPX
#define PHSTAT1_LLSTAT
#define PHSTAT1_JBSTAT
// ENC28J60 PHY PHCON2 Register Bit Definitions
#define PHCON2_FRCLINK
#define PHCON2_TXDIS
#define PHCON2_JABBER
#define PHCON2_HDLDIS
// ENC28J60 Packet Control Byte Bit Definitions
#define PKTCTRL_PHUGEEN
#define PKTCTRL_PPADEN
#define PKTCTRL_PCRCEN
#define PKTCTRL_POVERRIDE 0x01
// SPI operation codes
#define ENC28J60_READ_CTRL_REG
#define ENC28J60_READ_BUF_MEM
#define ENC28J60_WRITE_CTRL_REG
#define ENC28J60_WRITE_BUF_MEM
#define ENC28J60_BIT_FIELD_SET
#define ENC28J60_BIT_FIELD_CLR
#define ENC28J60_SOFT_RESET
// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
// buffer boundaries applied to internal 8K ram
// the entire available packet buffer space is allocated
// start with recbuf at 0/
#define RXSTART_INIT
// receive buffer end
#define RXSTOP_INIT
(0x1FFF-0x0600-1)
// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
#define TXSTART_INIT
(0x1FFF-0x0600)
// stp TX buffer at end of mem
#define TXSTOP_INIT
// max frame length which the conroller will accept:
MAX_FRAMELEN
// (note: maximum ethernet frame length would be 1518)
//#define MAX_FRAMELEN
uint8_t enc28j60ReadOp(uint8_t op, uint8_t address);
// functions
extern uint8_t enc28j60ReadOp(uint8_t op, uint8_t address);
extern void enc28j60WriteOp(uint8_t op, uint8_t address, uint8_t data);
extern void enc28j60ReadBuffer(uint16_t len, uint8_t* data);
extern void enc28j60WriteBuffer(uint16_t len, uint8_t* data);
extern void enc28j60SetBank(uint8_t address);
extern uint8_t enc28j60Read(uint8_t address);
extern void enc28j60Write(uint8_t address, uint8_t data);
extern void enc28j60PhyWrite(uint8_t address, uint16_t data);
extern void enc28j60clkout(uint8_t clk);
extern void enc28j60SpiInit(void);//////
extern void enc28j60Init(uint8_t* macaddr);
extern void enc28j60PacketSend(uint16_t len, uint8_t* packet);
extern uint16_t enc28j60PacketReceive(uint16_t maxlen, uint8_t* packet);
extern uint8_t enc28j60getrev(void);
extern uint8_t enc28j60hasRxPkt(void);
extern uint8_t enc28j60linkup(void);
extern void enc28j60EnableBroadcast( void );
extern void enc28j60DisableBroadcast( void );
extern void enc28j60EnableMulticast( void );
extern void enc28j60DisableMulticast( void );
extern void enc28j60PowerDown(void);
extern void enc28j60PowerUp(void);
#endif /* __ENC28J60_H */
拍了个小视频：
再结合点传感器，或许会发现有点智能家居的影子！
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